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19-2396; Rev 0; 4/02
Quad Bus LVDS Transceiver in 44 QFN
General Description
The MAX9158 is a quad bus LVDS (BLVDS) transceiver for heavily loaded, half-duplex multipoint buses. A 44lead QFN package and flow-through pinout allow the transceiver to be placed near the connector. The MAX9158 drives LVDS levels into a 27 load (double terminated, heavily loaded LVDS bus) at up to 200Mbps. An input fail-safe circuit ensures the receiver output is high when the differential inputs are open, or undriven and shorted, or undriven and terminated. The MAX9158 operates from a single 3.3V supply, consuming 77mA supply current with drivers enabled, and 19.9mA with drivers disabled. The MAX9158's high-impedance I/Os (except for receiver outputs) when VCC = 0V or open, combined with glitchfree power-up and power-down, allow hot swapping of cards in multicard bus systems; 7.3pF (max) BLVDS I/O capacitance minimizes bus loading. The MAX9158 is offered in a 7mm 7mm 44-lead QFN package, and is fully specified for the -40C to +85C extended temperature range. Refer to the MAX9157 data sheet for a quad BLVDS transceiver with hysteresis in 32lead QFN and TQFP packages. Refer to the MAX9129 data sheet for a quad BLVDS driver, ideal for dual multipoint full-duplex buses. o 44-Lead QFN Package o 1ns (min) Driver Transition Time (0% to 100%) Minimizes Reflections o Guaranteed 7.3pF (max) Bus Load Capacitance o Glitch-Free Power-Up and Power-Down o Hot-Swappable, High-Impedance I/O with VCC = 0V or Open o Guaranteed 200Mbps Driver Data Rate o Low-Jitter Fail-Safe Circuit o Flow-Through Pinout
Features
MAX9158
Ordering Information
PART MAX9158EGM TEMP RANGE -40C to +85C PIN-PACKAGE 44 QFN (7mm 7mm)
Pin Configuration
RO4 DIN4 RO3 DIN3 GND RO2 DIN2 RO1
41 40 39 38 37 36
44
43
42
35
DIN1
N.C.
TOP VIEW (LEADS UNDER PACKAGE)
Applications
Add/Drop Muxes Digital Cross-Connects Network Switches/Routers Cellular Phone Base Stations DSLAMs Multipoint Buses
N.C. N.C. VCC GND RE34 VCC AVCC DE34 AGND AVCC N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
34 33 32 31 30 29
N.C. N.C. N.C. GND VCC RE12 GND AVCC DE12 AGND N.C. N.C.
MAX9158EGM
28 27 26 25 24 23
Functional Diagram appears at end of data sheet.
Typical Operating Circuit
MAX9158 CARD 1 MAX9158 CARD 15 MAX9158 CARD 16
1in CARD SPACING
Rt = 54
DO4+/RIN4+ DO3-/RIN3DO3+/RIN3+ AGND DO2-/RIN2DO2+/RIN2+
QFN
DO1-/RIN1DO1+/RIN1+ AVCC
DO4-/RIN4-
Rt = 54
________________________________________________________________ Maxim Integrated Products
1
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
ABSOLUTE MAXIMUM RATINGS
VCC, AVCC to GND................................................-0.3V to +4.0V DO_+/RIN_+, DO_-/RIN_- to GND ........................-0.3V to +4.0V DIN_, DE_, RE_ to GND.........................................-0.3V to +4.0V RO_ to GND................................................-0.3V to (VCC + 0.3V) AGND to GND .......................................................-0.3V to +0.3V Short-Circuit Duration (DO_+/RIN_+, DO_-/RIN_-) ....Continuous Continuous Power Dissipation (TA = +70C) 44-Lead QFN (derate 24.3mW/C above +70C) ......2105mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C ESD Protection Human Body Model (DO_+/RIN_+, DO_-/RIN_-).............4kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 27 1%, receiver differential input voltage |VID| = 0.1V to 3.0V, receiver input common-mode voltage VCM = 0.05V to 2.4V, receiver input voltage range = 0V to 3.0V, DE_ = high, RE_ = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25C.) (Notes 1 and 2)
PARAMETER BLVDS (DO_+/RIN_+, DO_-/RIN_-) Differential Input High Threshold Differential Input Low Threshold Input Current Input Resistance Power-Off Input Current Differential Output Voltage Change in Magnitude of VOD for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output High Voltage Output Low Voltage VTH VTL IIN+, IINRIN1 RIN2 IINO+, IINOVOD VOD VOS VOS VOH VOL DE_ = low DE_ = low 0.1V VID 0.6V, DE_ = low 0.6V Output Short-Circuit Current
IOS
2
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Quad Bus LVDS Transceiver in 44 QFN
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 27 1%, receiver differential input voltage |VID| = 0V.1V to 3.0V, receiver input common-mode voltage VCM = 0.05V to 2.4V, receiver input voltage range = 0V to 3.0V, DE_ = high, RE_ = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25C.) (Notes 1 and 2)
PARAMETER Differential Output Short-Circuit Current Magnitude (Note 3) Capacitance at Bus Pins (Note 3) LVCMOS/LVTTL OUTPUTS (RO_) Open, undriven short, or undriven 27 parallel termination VID = 100mV Output Low Voltage Dynamic Output Current Output Short-Circuit Current (Note 4) Output High-Impedance Current Capacitance at Receiver Output (Note 3) Input High Voltage Input Low Voltage Input Current Power-Off Input Current SUPPLY Supply Current Drivers and Receivers Enabled Supply Current Drivers Enabled and Receivers Disabled Supply Current Drivers Disabled and Receivers Enabled Supply Current Drivers Disabled and Receivers Disabled ICC ICCD ICCR ICCZ DE_ = high, RE_ = low, RL = 27 DE_ = high, RE_ = high, RL = 27 DE_ = low, RE_ = low DE_ = low, RE_ = high 77 77 19.9 19.9 95 95 30 30 mA mA mA mA VOL IOD IOS IOZ COUTPUT IOL = 4.0mA, VID = -100mV, DE_ = low VID = 100mV, VRO_ = VCC - 1.0V, DE_ = low VID = -100mV, VRO_ = 1.0V, DE_ = low VID = 100mV, VRO_ = 0V, DE_ = low RE_ = high, VRO = 0V or VCC Capacitance from RO_ to GND, VCC = 3.6V or 0V 2.0 GND VDE_, VRE_, VDIN_ = high or low VDE_, VRE_, VDIN_ = 3.6V or 0V, VCC = 0V or open -20 -20 -10 -15 12 VCC 0.3 VCC 0.3 VCC 0.138 VCC 0.138 0.176 -25.8 20.7 -45 0.1 0.25 -40 40 -130 +10 4.6 V mA mA A pF SYMBOL IOSD COUTPUT CONDITIONS DIN_ = high or low, VOD = 0V Capacitance from DO_+/RIN_+ or DO_-/RIN_- to GND, VCC = 3.6V or 0V MIN TYP 14.8 MAX 30 7.3 UNITS mA pF
MAX9158
Output High Voltage
VOH
IOH = -4.0mA, DE_ = low
V
LVCMOS/LVTTL INPUTS (DIN, DE, RE) VIH VIL IIN IINO VCC 0.8 +20 +20 V V A A
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 27 1%, receiver differential input voltage |VID| = 0.15V to VCC, receiver input voltage range = 0V to VCC, input frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to VCC with 2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage VCM = 0.075V to 2.4V, DE_ = high, RE_ = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25C.) (Notes 3 and 5)
PARAMETER DRIVER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew | tPHLD - tPLHD | (Note 6) Channel-to-Channel Skew (Note 7) Chip-to-Chip Skew (Note 8) Chip-to-Chip Skew (Note 9) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 10) RECEIVER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew | tPHLD tPLHD | (Note 6) Channel-to-Channel Skew (Note 7) Chip-to-Chip Skew (Note 8) Chip-to-Chip Skew (Note 9) Rise Time tPHLD tPLHD tSKD1 tCCSK tSKD2 tSKD3 tTLH DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF DE_ = low, Figures 7, 8; CL = 15pF 0.5 1.09 1.5 1.5 2.21 2.13 74 96 0.63 3.5 3.5 250 350 1.6 2.0 1.6 ns ns ps ps ns ns ns tPHLD tPLHD tSKD1 tCCSK tSKD2 TSKD3 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 3, 4 RE_ = high, CL = 10pF, Figures 5, 6 RE_ = high, CL = 10pF, Figures 5, 6 RE_ = high, CL = 10pF, Figures 5, 6 RE_ = high, CL = 10pF, Figures 5, 6 RE_ = high, CL = 10pF, Figures 5, 6 100 0.6 0.6 1.07 1.10 2.8 2.8 4.6 4.5 1.2 1.1 1.96 1.87 91 119 0.45 2.5 2.4 250 350 0.90 1.4 1.4 1.4 5 5 6 6 ns ns ps ps ns ns ns ns ns ns ns ns MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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Quad Bus LVDS Transceiver in 44 QFN
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 27 1%, receiver differential input voltage |VID| = 0.15V to VCC, receiver input voltage range = 0V to VCC, input frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to VCC with 2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage VCM = 0.075V to 2.4V, DE_ = high, RE_ = low, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, and TA = +25C.) (Notes 3 and 5)
PARAMETER Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 10) SYMBOL tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS DE_ = low, Figures 7, 8, CL = 15pF DE_ = low, RL = 500, CL = 15pF, Figures 9, 10 DE_ = low, RL = 500, CL = 15pF, Figures 9, 10 DE_ = low, RL = 500, CL = 15pF, Figures 9, 10 DE_ = low, RL = 500, CL = 15pF, Figures 9, 10 DE_ = low, CL = 15pF 100 MIN 0.7 TYP 1.24 6.0 6.5 4.3 4.3 MAX 1.8 8 8 7 7 UNITS ns ns ns ns ns MHz
MAX9158
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Guaranteed by design and characterization. Note 4: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 5: CL includes scope probe and test fixture capacitance. Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |. Note 7: tCCSK is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 8: tSKD2 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 9: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 10: Meets data sheet specifications while operating at minimum fMAX rating.
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
Typical Operating Characteristics
(VCC = 3.3V, RL = 27, driver CL = 10pF, receiver CL = 15pF, |VID| = 200mV, VCM = 1.2V, fIN = 20MHz, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. FREQUENCY
DIFFERENTIAL OUTPUT VOLTAGE (V) FOUR CHANNELS DRIVEN
MAX9158 toc01
DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
MAX9158 toc02
DIFFERENTIAL OUTPUT VOLTAGE vs. OUTPUT LOAD
DIFFERENTIAL OUTPUT VOLTAGE (V) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
MAX9158 toc03
101 96 SUPPLY CURRENT (mA) 91 86
0.401
2.0
0.400
VCC = 3.6V
0.399
VCC = 3.3V 81 76 71 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) VCC = 3.0V
0.398
0.397
0.396 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
0 15 45 75 105 135 OUTPUT LOAD ()
DRIVER TRANSITION TIME vs. LOAD CAPACITANCE
MAX9158 toc04
DRIVER TRANSITION TIME vs. TEMPERATURE
MAX9158 toc05
1.3
1.3 1.2 tTHL 1.1 1.0 0.9 0.8 tTLH
DRIVER TRANSITION TIME (ns)
1.2 tTHL tTLH
1.1
1.0 5 10 15 20 25 LOAD CAPACITANCE (pF)
DRIVER TRANSITION TIME (ns)
0.7 -40 -15 10 35 60 85 TEMPERATURE (C)
DRIVER TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9158 toc06
RECEIVER TRANSITION TIME vs. LOAD CAPACITANCE
MAX9158 toc07
1.20 1.15 1.10 1.05 1.00 0.95 0.90 3.0 3.1 3.2 3.3 3.4 3.5 tTLH
3.0 RECEIVER TRANSITION TIME (ns) 2.5 tTHL 2.0 1.5 1.0 0.5 0
DRIVER TRANSITION TIME (ns)
tTHL
tTLH
3.6
5
10
15
20
25
30
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
6
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Quad Bus LVDS Transceiver in 44 QFN
Pin Description
PIN 1, 2, 11, 12, 23, 24, 32, 33, 34, 44 3, 6, 30 4, 28, 31, 39 5 7, 10, 22, 27 8 9, 17, 25 13 14 15 16 18 19 20 21 26 29 35 36 37 38 40 41 42 43 EP NAME N.C. VCC GND RE34 AVCC DE34 AGND DO4-/RIN4DO4+/RIN4+ DO3-/RIN3DO3+/RIN3+ DO2-/RIN2DO2+/RIN2+ DO1-/RIN1DO1+/RIN1+ DE12 RE12 DIN1 RO1 DIN2 RO2 DIN3 RO3 DIN4 RO4 EXPOSED PAD FUNCTION No Connection. Not internally connected. Digital Power Supply Digital Ground Receiver Channels 3 and 4 Enable (Enable Low). Drive RE34 low to enable receiver channels 3 and 4. Internal pullup to VCC. Analog Power Supply. Connect to board VCC. Driver Channels 3 and 4 Enable (Enable High). Drive DE34 high to enable driver channels 3 and 4. Internal pullup to VCC. Analog Ground. Connect to board ground. Channel 4 Inverting BLVDS Input/Output Channel 4 Noninverting BLVDS Input/Output Channel 3 Inverting BLVDS Input/Output Channel 3 Noninverting BLVDS Input/Output Channel 2 Inverting BLVDS Input/Output Channel 2 Noninverting BLVDS Input/Output Channel 1 Inverting BLVDS Input/Output Channel 1 Noninverting BLVDS Input/Output Driver Channels 1 and 2 Enable (Enable High). Drive DE12 high to enable driver channels 1 and 2. Internal pullup to VCC. Receiver Channels 1 and 2 Enable (Enable Low). Drive RE12 low to enable receiver channels 1 and 2. Internal pullup to VCC. Driver Channel 1 Input Receiver Channel 1 Output Driver Channel 2 Input Receiver Channel 2 Output Driver Channel 3 Input Receiver Channel 3 Output Driver Channel 4 Input Receiver Channel 4 Output Exposed Pad. Solder exposed pad to GND.
MAX9158
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
Detailed Description
The MAX9158 is a four-channel, 200Mbps, 3.3V BLVDS transceiver in a 44-lead QFN package, ideal for driving heavily loaded multipoint buses, typically 16 to 20 cards plugged into a backplane. The MAX9158 receivers accept a differential input and have a fail-safe input circuit. The devices detect differential signals as low as 100mV and as high as VCC. The MAX9158 driver outputs use a current-steering configuration to generate a 9.25mA to 17mA output current. This current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited. The MAX9158 current-steering output requires a resistive load to terminate the signal and complete the transmission loop. Because the devices switch the direction of current flow and not voltage levels, the output voltage swing is determined by the value of the termination resistor multiplied by the output current. With a typical 14.75mA output current, the MAX9158 produces a 398mV output voltage when driving a bus terminated with two 54 resistors (14.75mA 27 = 398mV). Logic states are determined by the direction of current flow through the termination resistor.
Effect of Capacitive Loading
The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane. The reduction in characteristic impedance is approximated by the following formula: ZDIFF-loaded = ZDIFF-unloaded SQRT [Co / (Co + N CL / L)] where: ZDIFF-unloaded = unloaded differential characteristic impedance Co = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads L = trace length For example, if Co = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDIFF-unloaded = 120, the loaded differential impedance is: ZDIFF-loaded = 120 SQRT [2.5pF / (2.5pF + 18 x 10pF / 18in)] ZDIFF-loaded = 54 In this example, capacitive loading reduces the characteristic impedance from 120 to 54. The load seen by
Fail-Safe Receiver Inputs
The fail-safe feature of the MAX9158 sets the receiver output high when the receiver differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the output and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver is in high impedance. A shorted input can occur because of a cable failure. When the input is driven with a differential signal with a common-mode voltage of 0.05V to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high (Figure 1).
VCC RIN2
VCC - 0.3V DO_+/RIN_+ RIN1 RO_ RIN1 D0_-/RIN_MAX9158
Figure 1. Internal Fail-Safe Circuit
8
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Quad Bus LVDS Transceiver in 44 QFN
a driver located on a card in the middle of the bus is 27 because the driver sees two 54 loads in parallel. A typical LVDS driver (rated for a 100 load) would not develop a large enough differential signal to be reliably detected by an LVDS receiver. The MAX9158 BLVDS drivers are designed and specified to drive a 27 load to differential voltage levels of 250mV to 460mV. A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. The MAX9158 driver outputs are current-source drivers and drive larger differential signal levels into loads lighter than 27 and smaller levels into loads heavier than 27 (see Typical Operating Characteristics curves). To keep loading from reducing bus impedance below the rated 27 load, PC board traces can be designed for higher unloaded characteristic impedance.
Applications Information
Supply Bypassing
Bypass each supply pin with high-frequency surfacemount ceramic 0.1F and 1nF capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the device.
MAX9158
Termination
In the example given in the Effect of Capacitive Loading section, the loaded differential impedance of a bus is reduced to 54. Since the bus can be driven from any card position, the bus must be terminated at each end. A parallel termination of 54 at each end of the bus placed across the traces that make up the differential pair provides a proper termination. The total load seen by the driver is 27. The MAX9158 drives higher differential signal levels into lighter loads. (See the Differential Output Voltage vs. Output Load graph in the Typical Operating Characteristics section.) A multidrop bus with the driver at one end and receivers connected at regular intervals along the bus has a lowered impedance due to capacitive loading. Assuming a 54 impedance, the multidrop bus can be terminated with a single, parallel-connected 54 resistor at the far end from the driver. Only a single resistor is required because the driver sees one 54 differential trace. The signal swing is larger with a 54 load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading).
Effect of Transition Times
For transition times (measured from 0% to 100%) shorter than the delay between capacitive loads, the loads are seen as low-impedance discontinuities from which the driven signal is reflected. Reflections add and subtract from the signal being driven, causing jitter and decreased noise margin. The MAX9158 output drivers are designed for a minimum transition time of 1ns (rated 0.6ns from 20% to 80%, or 1ns from 0% to 100%) to reduce reflections while being fast enough for high-speed backplane data transmission.
Power-On Reset
The power-on reset voltage of the MAX9158 is typically 2.25V. When the supply falls below this voltage, the devices are disabled and the receiver inputs/driver outputs are in high impedance. The power-on reset ensures glitch-free power-up and power-down, allowing hot swapping of cards in a multicard bus system without disrupting communications.
Table 1. I/O Enable Functional Table
MODE SELECTED Driver Mode Receiver Mode High-Impedance Mode Loopback Mode DE_ H L L H RE_ H L H L
Operating Modes
The MAX9158 features driver/receiver enable inputs that select the bus I/O function (Table 1). Tables 2 and 3 show the driver and receiver operating modes.
Table 2. Driver Mode
INPUTS DE_ H H L DIN_ L H X L H Z OUTPUTS DO_+/RIN_+ DO_-/RIN_H L Z
Input Internal Pullup/Pulldown Resistors
The MAX9158 includes pullup or pulldown resistors (300k) to ensure that unconnected inputs are defined (Table 4).
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
Table 3. Receiver Mode
INPUTS RE_ L L VID = (VDO_+/RIN_+) - (VDO_-/RIN_-) VID < -100mV VID > 100mV Fail-safe operation guaranteed when DO_+/RIN_+ and DO_-/RIN_- are open, undriven and shorted, or undriven and parallel terminated X OUTPUTS RO_ L H
Avoid the use of unbalanced cables, such as ribbon cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the receiver.
Board Layout
H
L
H
Z
A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep the LVTTL/LVCMOS and BLVDS signals separated to prevent coupling.
Table 4. Input Internal Pullup/Pulldown Resistors
PIN DE12 DE34 RE12 RE34 DIN_ INTERNAL RESISTOR Pullup to VCC Pullup to VCC Pullup to VCC Pullup to VCC None (floating)
VCC GND DIN_
D0_+/RIN_+
RL/2 VOS RL/2 VOD
DO_-/RIN_-
Traces, Cables, and Connectors
The characteristics of input and output connections affect the performance of the MAX9158. Use controlledimpedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the traces of a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between traces of a differential pair to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
Figure 2. Driver VOD and VOS Test Circuit
CL
VO
S
DO_+/RIN_+ GENERATOR DIN_ RL DO_-/RIN_CL
50
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
10
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
VCC DIN_ 50% 50% 0V tPLHD DO_-/RIN_0V DIFFERENTIAL DO_+/RIN_+ 0V VOL tPHLD VOH
CL
DO_+/RIN_+ VCC GND DE_ GENERATOR RL/2 50
0V 20% tTHL
DIN_
RL/2
+1.2V
80% 0V VOD 20% tTLH
80%
DO_-/RIN_1/4 MAX9158 CL
VOD = (VDO_+/RIN_+ - VDO_-/RIN_-)
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Figure 5. Driver High-Impedance Delay Test Circuit
DE_ 50% 50%
VCC
0V tPHZ D0_+/RIN_+ WHEN DIN_ = VCC DO_-/RIN_- WHEN DIN_ = 0V 50% 50% 1.2V 1.2V 50% DO_+/RIN_+ WHEN DIN_ = 0V DO_-/RIN_- WHEN DIN_ = VCC 50% VOL tPLZ tPZL tPZH VOH
Figure 6. Driver High-Impedance Delay Waveform
DO_+/RIN_+ PULSE GENERATOR RO_ DO_-/RIN_CL
50*
50*
RECEIVER ENABLED 1/4 MAX9158
*50 REQUIRED FOR PULSE GENERATOR TERMINATION.
Figure 7. Receiver Transition Time and Propagation Delay Test Circuit
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Quad Bus LVDS Transceiver in 44 QFN MAX9158
DO_-/RIN_0V (DIFFERENTIAL) DO_+/RIN_+ tPLHD tPHLD VOH 80% 80% VID 0V (DIFFERENTIAL)
50%
50%
20% RO_ tTLH tTHL
20% VOL
Figure 8. Receiver Transition Time and Propagation Delay Timing Diagram
VCC S1
DO_+/RIN_+ DO_-/RIN_GENERATOR RE_ 50 1/4 MAX9158 CL INCLUDES LOAD AND TEST FIXTURE CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
RL RO_ CL
Figure 9. Receiver High-Impedance Delay Test Circuit
VCC 50% RE_ tPZL tPLZ RO_ WHEN VID = -100mV RO_ WHEN VID = +100mV 0.5V tPHZ 0.5V 50% GND tPZH VOH VCC 50% VOL 50% 0V
Figure 10. Receiver High-Impedance Waveforms 12 ______________________________________________________________________________________
Quad Bus LVDS Transceiver in 44 QFN
Functional Diagram
DO1+/RIN1+ DIN1 DE12 RO1 RE12 DO2+/RIN2+ DIN2 DO2-/RIN2RO2 DO1-/RIN1-
Chip Information
TRANSISTOR COUNT: 1796 PROCESS: CMOS
MAX9158
DO3+/RIN3+ DIN3 DE34 RO3 RE34 DO4+/RIN4+ DIN4 DO4-/RIN4RO4 DO3-/RIN3-
MAX9158
______________________________________________________________________________________
13
Quad Bus LVDS Transceiver in 44 QFN MAX9158
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32, 44, 48L QFN .EPS
E2/2 (NE-1) X e
C L
D2 D D/2 k
C L
b D2/2
E/2
E
E2
k L DETAIL A e (ND-1) X e
C L
C L
L
L
e
e
A1
A2
A
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
1 2
A
14
______________________________________________________________________________________
Quad Bus LVDS Transceiver in 44 QFN
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9158
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
2 2
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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